A memory cell array having a three-dimensional structure has been studied for realizing next-generation non-volatile memory devices. For example, such a memory cell array may include bit lines extending in the direction perpendicular to an underlayer, and memory cells are disposed along each bit line. The memory cells may include a storage layer provided on the sidewall of the bit line.
It is possible to increase the memory capacity so as to provide the memory cells on both side of the bit line. However, when a pair of memory cells are disposed facing each other across the bit line, and one of the memory cells is selected for storing or erasing data, such an operation may influence the other memory cell. That is, a phenomenon so called “disturb” may induce an operational error, and reduces the reliability of the memory device.